EP1S20F672C7 vs EP1S20F484C7 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S20F672C7 sa pamamagitan ng Intel at EP1S20F484C7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S20F672C7 | EP1S20F484C7 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | Stratix | EP1S20 |
| Family | Altera Stratix FPGA | Stratix |
| Logic Elements (LEs) | 18,460 | — |
| Embedded Memory Bits | 1,669,248 | — |
| User I/O Pins | 426 | — |
| DSP Blocks | [DATA_NEEDED: DSP block count] | — |
| Packhaging | 672-ball FineLine BGA (35 x 35 mm, 1.27 mm pitch) | 484-ball FC-FBGA |
| Logic Family | CMOS, SRAM-based | — |
| Core Supply Voltage | 1.5 V | — |
| Temperature na Operasyon | 0C to 85C (commercial) | — |
| Speed Grade | C7 | C7 |
| Configuration Modes | JTAG, Passive Serial, Fast Passive Parallel, Active Serial | PS, PPS, PPA, JTAG |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Clock PLLs | Up to 10 | — |
| Process Technology | — | 130 nm CMOS |
| Core Voltage | — | 1.5 V |
| Logic Elements | — | 18,460 |
| Logic Array Blocks (LABs) | — | 1,846 |
| Total RAM Bits | — | 1,669,248 |
| Maximum I/O Pins | — | 361 |
| Package Size | — | 23 mm x 23 mm |
| Ball Pitch | — | 1.0 mm |
| Maximum Internal Frequency | — | 420.17 MHz |
| Hanay ng Temperature na Operasyon | — | 0 C to +85 C (Commercial) |
| Programming Voltage | — | 1.5 V (in-system via JTAG) |