EP1S30B956C6 vs EP1S40B956C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S30B956C6 sa pamamagitan ng Altera at EP1S40B956C6 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S30B956C6 | EP1S40B956C6 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 32,470 | — |
| Logic Array Blocks (LABs) | 3,247 | 4,125 |
| Embedded Memory Bits | 3,317,184 (approximately 3.4 Mbit) | — |
| Maximum User I/O | 683 | — |
| Process Technology | 130 nm CMOS | 0.13 um CMOS |
| Core Voltage (VCCINT) | 1.5 V | — |
| Temperature na Operasyon | 0 C to 85 C (Commercial) | 0C to 85C |
| Speed Grade | C6 | 6 (commercial, slowest) |
| Packhaging | 956-ball FCBGA (BGA-956), 40 x 40 mm, 1.27 mm pitch | BGA-956 (956-BBGA, FCBGA) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Maximum Internal Frequency | 450.05 MHz (per family datasheet) | — |
| DSP Blocks | Yes (Stratix DSP blocks) | Embedded multiplier blocks |
| PLLs | Up to 12 | Multiple phase-locked loops |
| Configuration Modes | Passive Serial (PS), Passive Parallel (PP), JTAG | — |
| Tindminan RoHS | Not confirmed - pre-RoHS part | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Lead-Free | Unknown | — |
| Logic Elements / Cells | — | 41,250 |
| CLB Equivalents / Registers | — | 46,970 |
| User I/O Pins | — | 683 |
| Package Size | — | 40 x 40 mm |
| Ball Pitch | — | 1.27 mm |
| Core Supply Voltage | — | 1.5 V |
| Logic Family | — | CMOS |
| Embedded Memory | — | TriMatrix (M512, M4K, M-RAM blocks) |
| Lead-Free / RoHS | — | Per Altera/Intel datasheet |