EP1S80B956C6AB vs EP1S80B956C6 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1S80B956C6AB sa pamamagitan ng Intel at EP1S80B956C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP1S80B956C6AB | EP1S80B956C6 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix | Stratix |
| Logic Elements (LEs) | 79,040 | — |
| Logic Cells | 79,040 | — |
| Process Technology | 130 nm | 130 nm CMOS |
| Core Voltage | 1.5 V | — |
| Maximum Operating Frequency | 450.05 MHz | — |
| User I/O Pins | 683 | — |
| Packhaging | 956-ball FCBGA | 956-BBGA, FCBGA, 40x40 mm |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | [DATA_NEEDED: RoHS compliance status] |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to 85C (TJ, commercial) |
| Memory Blocks | TriMatrix embedded RAM | — |
| DSP Blocks | Embedded DSP blocks (per Stratix family) | 22 |
| PLLs | Multiple PLLs for clock management | — |
| Configuration Method | SRAM-based, configured via JTAG or passive/active serial | — |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LE) | — | 79,040 |
| Logic Array Blocks (LAB) | — | 7,904 |
| Total Memory Bits | — | 7,427,520 (TriMatrix: M512 + M4K + M-RAM) |
| Embedded Memory | — | 6.336 Mbit |
| Maximum User I/O | — | 683 |
| Supply Voltage - Core | — | 1.425 V to 1.575 V |
| Speed Grade | — | -6 |
| Maximum Transceiver Rate | — | [DATA_NEEDED: high-speed transceiver data rate, GHz] |