EP1SGX25DF800C6N vs EP1SGX25DF800C5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP1SGX25DF800C6N sa pamamagitan ng Intel at EP1SGX25DF800C5N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP1SGX25DF800C6N - Stratix GX FPGA, 25K LE, 3.1875 Gbps SERDES | Intel / Altera
EP1SGX25DF800C6N Obsolete
Pagsanggunian na paghahambing
| Parametro | EP1SGX25DF800C6N | EP1SGX25DF800C5N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Stratix GX | Stratix GX |
| Logic Elements | 25,560 LEs | — |
| Maximum Transceiver Channels | 20 channels | — |
| Maximum Transceiver Data Rate | 3.1875 Gbps | 3.1875 Gbps per channel |
| Packhaging | FBGA-780 (FineLine BGA, 800-ball per JEDEC ordering code) | FBGA-800 (FineLine BGA, 31x31 mm) |
| Process Node | [DATA_NEEDED: process node] | — |
| Core Voltage | 1.5 V | — |
| Temperature na Operasyon | Commercial (0 C to +85 C) | 0C to +85C (commercial) |
| Speed Grade | 6 | C5 (commercial) |
| Configuration Method | Passive Serial / Passive Parallel / Active Serial / JTAG | — |
| Transceiver Encoding | 8B/10B | — |
| Clock Data Recovery (CDR) | Yes, integrated per channel | — |
| Uri ng Memory | TriMatrix embedded SRAM | — |
| DSP Blocks | Yes, embedded multiplier blocks | Embedded multiplier blocks (family-wide) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Lead Free | [DATA_NEEDED: lead free status] | — |
| Device Logic Elements | — | 25,660 (typical) |
| Transceiver Channels | — | 8 (full-duplex) |
| Process Technology | — | 130 nm |
| Supply Voltage (Core) | — | 1.5 V typical |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| On-Chip Memory (TriMatrix) | — | Approx. 2 Mbits total |
| PLLs | — | Up to 40 (device-wide) |
| Embedded 8b/10b Encoder/Decoder | — | Yes (one per transceiver channel) |
| PCI Express Hard IP | — | x1, x4 endpoints supported |
| Level ng MSL | — | [DATA_NEEDED: MSL Level] |
| Development Software | — | Quartus II (legacy) |