EP20K200FC484-3AA vs EP20K200FC484-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K200FC484-3AA sa pamamagitan ng Intel at EP20K200FC484-2X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K200FC484-2X - 200K Gates APEX 20K FPGA, 484-FBGA | Intel / Altera
EP20K200FC484-2X ObsoletePagsanggunian na paghahambing
| Parametro | EP20K200FC484-3AA | EP20K200FC484-2X |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX-20K | APEX 20K |
| Logic Elements | 8320 | — |
| Number of LABs/CLBs | 832 | — |
| Total RAM Bits | 106496 | — |
| Number of I/O Pins | 382 | — |
| Maximum Gates | 526000 | — |
| Volte ng Pagbibigay | 2.375 V to 2.625 V | — |
| Speed Grade | -3 | -2 (with LVDS support, "X" suffix) |
| Package Type | 484-BBGA (FineLine BGA) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to 85 °C (commercial) |
| Temperature ng Junction na Operasyon | [DATA_NEEDED: junction temperature range] | — |
| Configuration Interface | JTAG (IEEE 1149.1) / Serial | — |
| Process Technology | CMOS | 0.22 µm CMOS |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Lead Free | [DATA_NEEDED: lead-free status] | — |
| Series | — | EP20K200 |
| Device Type | — | FPGA (Field Programmable Gate Array) |
| Maximum Logic Elements | — | 8,320 cells |
| Typical System Gates | — | 200,000 |
| Embedded Memory (EAB) | — | 106,496 bits |
| Maximum User I/O | — | 382 |
| Number of Logic Elements | — | 8,320 |
| Propagation Delay | — | 3.0 ns |
| Maximum Internal Frequency | — | 200 MHz |
| Core Supply Voltage | — | 2.5 V |
| Packhaging | — | 484-pin FBGA (FineLine BGA), 1.0 mm pitch |
| Programmable I/O Standards | — | 1.8 V, 2.5 V, 3.3 V, LVTTL, LVCMOS, LVDS |
| JTAG Support | — | IEEE 1149.1 Boundary-Scan |