EP20K30EQC208-1 vs EP20K30EQC208-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K30EQC208-1 sa pamamagitan ng Altera at EP20K30EQC208-2 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K30EQC208-1 EP20K30EQC208-2
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Series APEX-20KE —
Family FPGA APEX 20K Family APEX 20KE
Number of Logic Elements/Cells 1200 —
Number of Gates 30000 (30K gates) —
Number of Macro Cells [DATA_NEEDED: Number of macro cells] —
Total RAM Bits 24576 —
Number of User I/O 125 —
Voltage - Supply 1.71 V to 1.89 V —
Core Voltage 1.8 V —
Technology 0.22 um —
Packhaging / Kaso 208-BFQFP —
Supplier Device Package 208-PQFP (28x28) —
Package Code FQFP —
Terminal Form Gull wing —
Number of Terminals 208 —
Terminal Pitch 0.50 mm —
Package Shape Square —
Uri ng Pagpapasok Surface Mount Surface Mount (PQFP with gull-wing leads)
Speed Grade -1 -2 (2.69 ns pin-to-pin)
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance status]
Device Logic — FPGA (SRAM-based)
Typical Gates — 30,000
Logic Elements — 1,200
Embedded Memory (RAM bits) — 24,576
Maximum User I/O — 125
Dedicated Inputs — 4
Packhaging — 208-BFQFP (PQFP-208)
Core Supply Voltage — 1.71 V to 1.89 V
I/O Standard — LVDS-compatible, 1.8 V / 2.5 V / 3.3 V (per bank)
Maksimum na Taktiko ng Oras — 160 MHz
Propagation Delay — 2.69 ns
Configuration Interface — IEEE 1149.1 JTAG, Passive serial, Active serial
Temperature na Operasyon — [DATA_NEEDED: operating temperature range]
Process Technology — 1.8 V CMOS, MultiCore architecture
Level ng MSL — [DATA_NEEDED: MSL rating]

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