EP20K400FI672-2 vs EP20K400FI672-2N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-2 sa pamamagitan ng Altera at EP20K400FI672-2N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400FI672-2 EP20K400FI672-2N
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family APEX-20K APEX 20K
Logic Elements 16640 —
Maximum Gates 400,000 gates —
User I/Os 502 —
Embedded Memory Bits 212992 212,992 bits
Number of Macros 1664 —
Process Technology 0.22 µm CMOS 0.22 µm CMOS
Core Supply Voltage 2.5 V —
Maximum Internal Frequency 200 MHz —
Propagation Delay 2.5 ns 3.1 ns
Temperature na Operasyon 0 °C to +85 °C (Commercial) Commercial (0 °C to +70 °C) [DATA_NEEDED: industrial variant]
Package Type 672-pin Fine-pitch Ball Grid Array (FBGA/FCBGA) —
PLLs (Phase-Locked Loops) 4 —
Configuration Modes JTAG, Passive Serial, Passive Parallel PS, PPS, PPA, JTAG
Tindminan RoHS Lead-free / RoHS Compliant Compliant (lead-free)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Typical Gates — 400,000
Logic Elements / Cells — 16,640
Maximum User I/O — 488
Embedded Array Blocks (EABs) — [DATA_NEEDED: EAB count per family datasheet]
Core Voltage — 2.5 V
Maximum Frequency — 200 MHz
Packhaging — 672-pin FC-FBGA (Flip-Chip Fine-pitch BGA)
Package Body Size — 27 x 27 mm
Terminal Pitch — 1.0 mm
Speed Grade — -2
Level ng Sensitivity sa Asid ng Moisture (MSL) — 3
Peak Reflow Temperature — 220 °C
Supported I/O Standards — LVTTL, LVCMOS, SSTL, HSTL

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