EP20K400FI672-3 vs EP20K400FI672-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3 sa pamamagitan ng Altera at EP20K400FI672-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-3 | EP20K400FI672-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | APEX 20K | — |
| Series | EP20K400 | APEX 20K |
| Logic Elements | 16640 | 212,992 |
| Total Gates | up to 400000 | — |
| Embedded RAM | 212992 bits | — |
| Maximum User I/O | 502 | — |
| Dedicated Inputs | 6 | 4 |
| Propagation Delay | 3.6 ns | 2.5 ns |
| Maksimum na Taktiko ng Oras | 833 MHz | — |
| Supply Voltage (Nominal) | 2.5 V | — |
| Supply Voltage Range | 2.375 V to 2.625 V | — |
| Process Technology | CMOS | CMOS |
| Package Type | PBGA (Plastic BGA) | — |
| Package Code | S-PBGA-B672 | — |
| Terminal Count | 672 | — |
| Terminal Pitch | 1.000 mm | — |
| Package Shape | Square BGA | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Configuration Interface | JTAG (IEEE 1149.1) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Industrial (per 'I' suffix) |
| Level ng MSL | 3 | 3 |
| Peak Reflow Temperature | 220 C | 220 C |
| Device Family | — | APEX-20K Field Programmable Gate Array |
| Typical Gates | — | 400,000 |
| Logic Array Blocks (LABs) | — | 16,640 |
| User I/O Pins | — | 502 |
| Total Terminals | — | 672 |
| Packhaging | — | 672-ball PBGA (FineLine BGA, 1.0 mm pitch) |
| Package Code (JEDEC) | — | S-PBGA-B672 |
| Core Supply Voltage (VCCINT) | — | 2.5 V nominal (2.375 V to 2.625 V) |
| Speed Grade | — | -1 |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |