EP20K400FI672-3X vs EP20K400FI672-2X Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400FI672-3X sa pamamagitan ng Altera at EP20K400FI672-2X sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
EP20K400FI672-3X ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EP20K400FI672-3X | EP20K400FI672-2X |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Maximum System Gates | 400,000 | — |
| Maximum Logic Elements | [DATA_NEEDED: exact LE count for EP20K400] | — |
| Maximum User I/O | 502 | — |
| Packhaging | 672-ball Fine-Pitch BGA (S-PBGA-B672) | 672-ball BGA (FI672) |
| Terminal Pitch | 1.000 mm | — |
| Nominal Core Voltage (VCCINT) | 2.5 V | — |
| VCCINT Range | 2.375 V to 2.625 V | — |
| Typical Propagation Delay | 3.6 ns | — |
| Maximum Internal Clock Frequency | 833 MHz | — |
| Technology | CMOS SRAM configuration cell | — |
| Speed Grade | -3 (high-performance tier) | -2X |
| Temperature Grade (X suffix) | Industrial / extended | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant (per Intel/Altera product page) | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 system gates |
| Embedded Memory | — | 212,992 bits |
| User I/O Pins | — | 496 |
| Package Code | — | BGA |
| Terminal Form | — | Ball |
| No. of Terminals | — | 672 |
| Package Shape | — | Square |
| Temperature na Operasyon | — | -40C to +85C (industrial) |
| Core Voltage | — | 1.8 V |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | — | SRAM (serial EPROM or JTAG) |
| JTAG Support | — | Yes (IEEE 1149.1) |
| Process Technology | — | 0.18 um CMOS, 6-metal |