EP20K400FI672-3X vs EP20K400FI672-2X 比較
詳細並排比較 EP20K400FI672-3X 由 Altera 與 EP20K400FI672-2X 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400FI672-3X - APEX 20K 400K Gates FPGA, 672-BGA | Altera/Intel
EP20K400FI672-3X ⚠ 最後購買機會
規格比較
| 參數 | EP20K400FI672-3X | EP20K400FI672-2X |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | APEX 20K | APEX 20K |
| Device Series | EP20K400 | — |
| Maximum System Gates | 400,000 | — |
| Maximum Logic Elements | [DATA_NEEDED: exact LE count for EP20K400] | — |
| Maximum User I/O | 502 | — |
| 封裝 | 672-ball Fine-Pitch BGA (S-PBGA-B672) | 672-ball BGA (FI672) |
| Terminal Pitch | 1.000 mm | — |
| Nominal Core Voltage (VCCINT) | 2.5 V | — |
| VCCINT Range | 2.375 V to 2.625 V | — |
| Typical Propagation Delay | 3.6 ns | — |
| Maximum Internal Clock Frequency | 833 MHz | — |
| Technology | CMOS SRAM configuration cell | — |
| Speed Grade | -3 (high-performance tier) | -2X |
| Temperature Grade (X suffix) | Industrial / extended | — |
| 濕度敏感等級 (MSL) | 3 | — |
| Peak Reflow Temperature | 220 C | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant (per Intel/Altera product page) | [DATA_NEEDED: RoHS compliance] |
| Logic Elements | — | 16,640 |
| Typical Gates | — | 400,000 system gates |
| Embedded Memory | — | 212,992 bits |
| User I/O Pins | — | 496 |
| Package Code | — | BGA |
| Terminal Form | — | Ball |
| No. of Terminals | — | 672 |
| Package Shape | — | Square |
| 工作溫度 | — | -40C to +85C (industrial) |
| Core Voltage | — | 1.8 V |
| I/O Voltage Support | — | 1.8V / 2.5V / 3.3V / 5V (MultiVolt) |
| Configuration Method | — | SRAM (serial EPROM or JTAG) |
| JTAG Support | — | Yes (IEEE 1149.1) |
| Process Technology | — | 0.18 um CMOS, 6-metal |