EP20K400GC655-2 vs EP20K400GC655-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2 sa pamamagitan ng Altera at EP20K400GC655-1 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 ObsoletePagsanggunian na paghahambing
| Parametro | EP20K400GC655-2 | EP20K400GC655-1 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212,992 |
| Maximum Internal Frequency | 200 MHz | 250 MHz |
| Speed Grade | -2 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | 3.3 V |
| LVDS Support | Yes | — |
| PLLs | 4 | — |
| Bilang ng Pin | 655 | 655 |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| Uri ng Pagpapasok | Through-Hole (CPGA) | Through-Hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead in ceramic package) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Propagation Delay | — | 2.5 ns |
| Packhaging | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |