EP20K400GC655-2 vs EP20K400GC655-1 比較
詳細並排比較 EP20K400GC655-2 由 Altera 與 EP20K400GC655-1 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP20K400GC655-1 - 400K Gate APEX 20K FPGA, 655-pin CPGA | Intel/Altera
EP20K400GC655-1 Obsolete規格比較
| 參數 | EP20K400GC655-2 | EP20K400GC655-1 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | APEX-20KC | EP20K400 |
| Family | APEX 20K | APEX 20K |
| Device Type | FPGA (Field Programmable Gate Array) | — |
| System Gates | 400,000 | — |
| Logic Cells / Elements | 16,640 | — |
| Total RAM Bits | 212,992 | 212,992 |
| Maximum Internal Frequency | 200 MHz | 250 MHz |
| Speed Grade | -2 | — |
| Process Technology | 0.22 µm CMOS | 0.22 µm CMOS |
| Core Supply Voltage | 2.5 V | 2.5 V |
| I/O Supply Voltage | 1.71 V to 1.89 V (MultiVolt) | 3.3 V |
| LVDS Support | Yes | — |
| PLLs | 4 | — |
| 腳位數 | 655 | 655 |
| Package Type | 655-BCPGA (CPGA-655) | — |
| Package Dimensions | 62.48 x 62.48 mm | — |
| 安裝類型 | Through-Hole (CPGA) | Through-Hole |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0 °C to +85 °C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Non-compliant (contains lead in ceramic package) |
| Logic Elements | — | 16,640 |
| Maximum Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Embedded System Blocks (ESBs) | — | 4 |
| Maximum User I/O | — | 502 |
| Dedicated Inputs | — | 6 |
| Propagation Delay | — | 2.5 ns |
| 封裝 | — | 655-pin CPGA (Ceramic Pin Grid Array) |
| Configuration Modes | — | Passive Serial, Passive Parallel Async, Passive Parallel Sync |
| Boundary Scan | — | IEEE 1149.1 (JTAG) |