EP20K400GC655-2V vs EP20K400GI655-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-2V sa pamamagitan ng Altera at EP20K400GI655-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K400GC655-2V - 400K Gate APEX-20KC FPGA 655-CPGA | Altera
EP20K400GC655-2V ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP20K400GC655-2V | EP20K400GI655-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Series | APEX-20KC | APEX 20K (EP20K400) |
| Family | APEX 20KC (1.8 V, LVDS) | — |
| Logic Elements | 16,640 | — |
| Total RAM Bits | 212,992 | — |
| System Gates | ~400,000 (typical marketing figure) | — |
| Number of I/O | [DATA_NEEDED: I/O count] | — |
| Core Voltage (VCCINT) | 2.375 V to 2.625 V (nominal 2.5 V) | — |
| Propagation Delay | 3.000 ns | 3.1 ns (typical) |
| Process Technology | CMOS, 0.18 um | — |
| LVDS Support | Yes | — |
| Packhaging | 655-CPGA (62.48 x 62.48 mm) | SPGA-655 (47 mm x 47 mm) |
| Package Type | Ceramic Pin Grid Array, through-hole | — |
| Uri ng Pagpapasok | Through-hole (CPGA) | Through-Hole / Socket |
| Speed Grade | -2 | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | -40C to +85C (industrial) |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free | unknown | — |
| Architecture | MultiCore (LUT + product-term + embedded memory) | — |
| Manufacturer | — | Altera Corporation |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Typical Gate Count | — | 400,000 gates |
| Logic Elements (LE) | — | 16,640 |
| Maximum User I/O | — | 496 |
| Dedicated Inputs | — | 6 |
| Number of Terminals | — | 655 |
| Nominal Supply Voltage | — | 2.5 V |
| Supply Voltage Range | — | 2.375 V to 2.625 V |
| Technology | — | CMOS SRAM |
| Moisture Sensitivity Level | — | 1 (per Altera family) |
| Configuration Method | — | JTAG, Passive Serial, Passive Parallel |
| I/O Standards Supported | — | LVTTL, LVCMOS, PCI, GTL+ |
| Embedded Memory | — | Embedded System Blocks (ESBs) |
| Katayuan ng Lifecycle | — | Obsolete (legacy Altera APEX 20K family) |