EP20K400GC655-3X vs EP20K400GI655-1X Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GC655-3X sa pamamagitan ng Altera at EP20K400GI655-1X sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400GC655-3X EP20K400GI655-1X
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series APEX-20KC —
Family APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) APEX 20K
Manufacturer Altera (now Intel FPGA) —
Logic Elements / Cells 16,640 —
System Gates 400,000 —
Total RAM Bits 212,992 bits —
Maximum Internal Frequency 167 MHz (speed grade -3) —
Process Technology 0.22 µm CMOS CMOS, SRAM-based configuration
Core Supply Voltage (VCCINT) 1.71 V to 1.89 V —
I/O Supply Voltage (VCCIO) 2.5 V (LVDS support per APEX 20KE datasheet) —
Packhaging / Kaso 655-BCPGA (CPGA655, 62.48 x 62.48 mm) —
Uri ng Pagpapasok Through-Hole (CPGA, ceramic) Through-Hole (PGA)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40 C to +85 C (industrial)
Speed Grade -3 (fastest) -1
Suffix Code -X (extended / ceramic CPGA variant) —
I/O Count [DATA_NEEDED: max user I/O] —
JTAG / Boundary Scan IEEE 1149.1 (per APEX 20K family) —
Tindminan RoHS [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] Compliant
Device — EP20K400
Logic Elements — 16640
Number of Terminals — 655
User I/O Lines — 502
Dedicated Inputs — 4
Package Type — Ceramic Pin Grid Array (CPGA)
Package Code (JESD-30) — S-CPGA-P655
Package Equivalence Code — SPGA655,47X47
Package Body Material — CERAMIC (metal-sealed co-fired)
Propagation Delay — 2.5 ns (typical for -1 grade)
Level ng Sensitivity sa Asid ng Moisture (MSL) — 1
Peak Reflow Temperature — 220 C

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