EP20K400GC655-3X vs EP20K400GI655-1X 比較
詳細並排比較 EP20K400GC655-3X 由 Altera 與 EP20K400GI655-1X 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP20K400GI655-1X - 400K Gate APEX 20K FPGA, 16640 Logic Elements, 655-Pin CPGA | Altera (Intel)
EP20K400GI655-1X Obsolete規格比較
| 參數 | EP20K400GC655-3X | EP20K400GI655-1X |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Series | APEX-20KC | — |
| Family | APEX 20K (MultiCore architecture, LUT + product-term + embedded memory) | APEX 20K |
| Manufacturer | Altera (now Intel FPGA) | — |
| Logic Elements / Cells | 16,640 | — |
| System Gates | 400,000 | — |
| Total RAM Bits | 212,992 bits | — |
| Maximum Internal Frequency | 167 MHz (speed grade -3) | — |
| Process Technology | 0.22 µm CMOS | CMOS, SRAM-based configuration |
| Core Supply Voltage (VCCINT) | 1.71 V to 1.89 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V (LVDS support per APEX 20KE datasheet) | — |
| 封裝 / 外殼 | 655-BCPGA (CPGA655, 62.48 x 62.48 mm) | — |
| 安裝類型 | Through-Hole (CPGA, ceramic) | Through-Hole (PGA) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40 C to +85 C (industrial) |
| Speed Grade | -3 (fastest) | -1 |
| Suffix Code | -X (extended / ceramic CPGA variant) | — |
| I/O Count | [DATA_NEEDED: max user I/O] | — |
| JTAG / Boundary Scan | IEEE 1149.1 (per APEX 20K family) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - ceramic CPGA historically non-RoHS] | Compliant |
| Device | — | EP20K400 |
| Logic Elements | — | 16640 |
| Number of Terminals | — | 655 |
| User I/O Lines | — | 502 |
| Dedicated Inputs | — | 4 |
| Package Type | — | Ceramic Pin Grid Array (CPGA) |
| Package Code (JESD-30) | — | S-CPGA-P655 |
| Package Equivalence Code | — | SPGA655,47X47 |
| Package Body Material | — | CERAMIC (metal-sealed co-fired) |
| Propagation Delay | — | 2.5 ns (typical for -1 grade) |
| 濕度敏感等級 (MSL) | — | 1 |
| Peak Reflow Temperature | — | 220 C |