EP20K400GI655-2 vs EP20K400GI655-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP20K400GI655-2 sa pamamagitan ng Altera at EP20K400GI655-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP20K400GI655-2 EP20K400GI655-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Altera Corporation —
Series APEX 20K (EP20K400) —
Device Type Field Programmable Gate Array (FPGA) —
Typical Gate Count 400,000 gates —
Logic Elements (LE) 16,640 —
Maximum User I/O 496 502
Dedicated Inputs 6 4
Number of Terminals 655 —
Packhaging SPGA-655 (47 mm x 47 mm) —
Nominal Supply Voltage 2.5 V —
Supply Voltage Range 2.375 V to 2.625 V —
Propagation Delay 3.1 ns (typical) 2.5 ns
Technology CMOS SRAM CMOS, SRAM-based
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (Industrial)
Uri ng Pagpapasok Through-Hole / Socket —
Moisture Sensitivity Level 1 (per Altera family) MSL 1
Configuration Method JTAG, Passive Serial, Passive Parallel —
I/O Standards Supported LVTTL, LVCMOS, PCI, GTL+ —
Embedded Memory Embedded System Blocks (ESBs) —
Tindminan RoHS [DATA_NEEDED: RoHS status] Compliant
Katayuan ng Lifecycle Obsolete (legacy Altera APEX 20K family) —
Family — APEX 20K
Device Series — EP20K400
Logic Elements — 16640
Typical Gates — 400000
Total Terminals — 655
Package Type — Ceramic Pin Grid Array (CPGA-655)
JESD-30 Package Code — S-CPGA-P655
Peak Reflow Temperature — 220 C
Programmability — In-system, JTAG boundary-scan (IEEE 1149.1)
Process Node — 0.18 micrometer CMOS

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