EP20K60ETC144-2N vs EP20K60EFC144-2XN Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP20K60ETC144-2N sa pamamagitan ng Intel at EP20K60EFC144-2XN sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP20K60EFC144-2XN - APEX-20KE FPGA 60K Gates 93 I/O 144-BGA | Intel/Altera
EP20K60EFC144-2XN NrndPagsanggunian na paghahambing
| Parametro | EP20K60ETC144-2N | EP20K60EFC144-2XN |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | APEX-20KE | APEX-20K (MultiCore Architecture) |
| Logic Elements | 2,560 | — |
| Typical Gates | 60,000 | — |
| Embedded Memory (ESB) | 32,768 bits (32 Kbits) | — |
| User I/Os | 92 | — |
| Core Voltage (VCCINT) | 1.71 V to 1.89 V (1.8 V nominal) | — |
| Speed Grade | -2 | -2 (per MPN suffix) |
| Internal Frequency (max) | 160 MHz | — |
| Propagation Delay | 1.72 ns | — |
| Process Technology | 0.22 µm CMOS | — |
| Packhaging | 144-pin TQFP (20 × 20 mm, 0.5 mm pitch) | — |
| Temperature na Operasyon | 0 °C to 85 °C (commercial) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Logic Family | CMOS | CMOS, SRAM-based LUT |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Series | — | APEX-20KE |
| Typical Gate Count | — | 60,000 gates |
| Logic Elements / Embedded Array Blocks | — | 2,560 |
| Embedded Memory (Bits) | — | 32,768 |
| Maximum User I/O | — | 93 |
| Number of I/O Banks | — | [DATA_NEEDED: number of I/O banks] |
| Core Supply Voltage (VCCINT) | — | 1.71 V to 1.89 V |
| I/O Supply Voltage (VCCIO) | — | [DATA_NEEDED: VCCIO range] |
| Package Type | — | 144-BGA (Fine-pitch Ball Grid Array) |
| Package Code (per MPN suffix) | — | FBGA / LBGA, 13x13 mm |
| Operating Temperature (TJ) | — | 0 C to +85 C (commercial) |
| Configuration Method | — | JTAG (IEEE 1149.1), Passive Serial, Parallel |