EP2A25F672I9 vs EP2A25F672I8N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I9 sa pamamagitan ng Intel at EP2A25F672I8N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP2A25F672I8N - APEX II FPGA 900K Gates 672-BGA | Intel / Altera
EP2A25F672I8N ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP2A25F672I9 | EP2A25F672I8N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | APEX II | APEX II |
| Manufacturer | Intel (formerly Altera) | — |
| Logic Elements (LEs) | 24,320 | — |
| System Gates (typical) | 900,000 | — |
| Maximum Operating Frequency | 236 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.15 µm all-layer copper-metal |
| Core Voltage (VCCINT) | 1.5 V | 1.5 V |
| Packhaging | 672-pin FC-FBGA | 672-ball FC-FBGA (FineLine BGA) |
| Bilang ng Pin | 672 | — |
| Temperature Grade | Industrial (-40 °C to +100 °C) | — |
| Speed Grade | 9 (fastest APEX II grade) | — |
| Embedded System Blocks (ESBs) | Yes (dual-port RAM/ROM) | — |
| Maximum User I/O | [DATA_NEEDED: max user I/O pin count] | — |
| Maximum Memory Bits | 422,400 bits | — |
| PLLs | 4 | — |
| Uri ng Pagpapasok | Surface Mount (flip-chip BGA) | — |
| Peak Reflow Temperature | 220 °C (per distributor listing) | — |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | 3 | — |
| Tindminan RoHS | Unknown (legacy 2000s part; verify lot certificate) | unknown |
| Device | — | EP2A25 |
| Logic Elements | — | 24,320 |
| Gates | — | 900,000 |
| Embedded Memory (bits) | — | 622,592 |
| User I/Os | — | 492 |
| Package Size | — | 27 x 27 mm |
| Ball Pitch | — | 1 mm |
| Metal Layers | — | Up to 8 |
| Internal Frequency (max) | — | 333 MHz |
| Propagation Delay | — | 1.69 ns |
| Temperature na Operasyon | — | 0 °C to 85 °C |
| Logic Family | — | CMOS |
| I/O Standards Supported | — | True-LVDS, LVPECL, PCML, HyperTransport |
| Configuration Method | — | SRAM-based (Altera Quartus II) |
| Lead-Free | — | unknown |