EP2A40F672C9 vs EP2A40F672C6 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A40F672C9 sa pamamagitan ng Altera at EP2A40F672C6 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A40F672C9 EP2A40F672C6
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family APEX II APEX II
Device Family APEX II PLD —
Logic Elements / Cells 38,400 —
System Gates 1.5 M —
Macros 2,560 —
User I/Os 492 —
Bilang ng Pins 672 —
Packhaging 672-BBGA, FC-FBGA (FineLine) 672-ball FineLine BGA (FBGA-672)
Package Size 27 mm × 27 mm, 1 mm ball pitch —
Core Voltage 1.5 V —
Process Technology 0.15 µm all-layer copper, up to 8 metal layers 0.18-micron CMOS
Logic Family CMOS —
Propagation Delay 1.55 ns —
Internal Speed Grade 366 MHz —
Temperature na Operasyon 0 °C to 85 °C (commercial) Commercial (0C to +85C)
I/O Standards Supported True-LVDS, LVPECL, PCML, HyperTransport —
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device — EP2A40
Logic Elements (typical) — 40,000
Maximum System Gates — [DATA_NEEDED: maximum system gates]
Embedded System Blocks (ESBs) — [DATA_NEEDED: ESB count]
Maximum User I/O Pins — [DATA_NEEDED: max user I/O count]
Speed Grade — C6 (commercial)
Configuration Memory — SRAM-based
JTAG Support — Yes (IEEE 1149.1)
PLL Support — Yes
Lead-Free — [DATA_NEEDED: lead-free status]
Lifecycle — Obsolete / EOL (per Intel/Altera product discontinuation notice)

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