EP2AGZ300FF35C4G vs EP2AGZ300FF35I4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2AGZ300FF35C4G sa pamamagitan ng Intel at EP2AGZ300FF35I4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2AGZ300FF35C4G | EP2AGZ300FF35I4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Arria II GZ | Arria II GZ |
| Logic Elements | 300,000 | 298,000 |
| Adaptive Logic Modules (ALMs) | 119,000 | — |
| Embedded Memory | 16,624 Kbit (M9K + M144K) | M20K blocks (distributed) |
| Embedded 18x18 Multipliers | 736 | — |
| User I/O Pins | 554 | — |
| Transceivers | 12 channels | 12.5 Gbps integrated |
| Max Transceiver Data Rate | 6.375 Gbps (C4 speed grade) | — |
| Packhaging | 1152-ball FineLine BGA (FBGA-1152), 35x35 mm | 1152-ball FC-FBGA (FF35) |
| Temperature na Operasyon | 0°C to +85°C (commercial C4 grade) | — |
| Speed Grade | 4 | — |
| Process Technology | 40 nm TSMC | 40 nm |
| Core Voltage | 0.85 V to 1.1 V | 0.9 V |
| PLLs | 8 (up to 4 per quadrant) | — |
| Global Clock Networks | 16 | — |
| PCIe Hard IP | PCIe Gen2 x4 | — |
| Hard Memory Controller | DDR3 up to 800 MHz | — |
| Configuration | Passive Serial, Fast Passive Parallel, JTAG | — |
| Tindminan RoHS | Compliant | Compliant |
| Level ng MSL | 3 (168 hours) | — |
| Configurable Logic Blocks (LABs/CLBs) | — | 11,920 |
| Maximum User I/O | — | 554 |
| Operating Frequency (Max) | — | 500 MHz |
| Temperature Grade | — | Industrial (-40 C to +100 C) |
| Number of Pins/Balls | — | 1152 |
| Terminal Form | — | Ball (BGA) |
| DSP Blocks | — | Hard DSP columns (variable precision) |
| PCIe Support | — | PCIe Gen2 hard IP |
| Uri ng Pagpapasok | — | Surface Mount (flip-chip BGA) |
| Lead-Free | — | Yes |