EP2S30F672C4 vs EP2S30F672I4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S30F672C4 sa pamamagitan ng Intel at EP2S30F672I4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S30F672C4 | EP2S30F672I4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Series | Stratix II | Stratix II |
| Logic Elements / Cells | 33,880 | — |
| Total RAM Bits | 1,369,728 | 1369728 |
| Number of I/O | 500 | 500 |
| Packhaging | 672-BBGA, FCBGA (27x27 mm) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Core Voltage - Supply | 1.15 V to 1.25 V | — |
| Process Technology | 90 nm | 90 nm CMOS |
| Maximum Core Frequency (datasheet benchmark) | 711 MHz | — |
| Temperature na Operasyon | 0C to +85C (commercial, 'C' speed grade) | -40C to +100C (Industrial) |
| Embedded DSP Blocks | 16 (Stratix II S30 tier) | — |
| Number of PLLs | [DATA_NEEDED: PLL count for S30 tier] | 6 |
| Number of Global Clock Networks | [DATA_NEEDED: global clock network count] | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: confirm RoHS compliance on part label] |
| Lead-Free | Yes | — |
| Logic Elements | — | 33880 |
| Logic Array Blocks (LABs) | — | 1694 |
| DSP Blocks | — | 12 (per datasheet, family range) |
| Voltage - Supply | — | 1.2 V core, separate I/O bank VCCIO |
| Packhaging / Kaso | — | 672-BBGA, FCBGA (FBGA-672) |
| Package Dimensions | — | 35 x 35 mm |
| Ball Pitch | — | 1.0 mm |
| Configuration | — | JTAG, serial, parallel (Stratix II scheme) |
| Level ng MSL | — | 3 (per JEDEC J-STD-020) |