EP2S30F672I4 vs EP2S30F672C4 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP2S30F672I4 sa pamamagitan ng Intel at EP2S30F672C4 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP2S30F672I4 | EP2S30F672C4 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | Stratix II | Stratix II |
| Manufacturer | Intel (formerly Altera) | Intel (formerly Altera) |
| Logic Elements | 33880 | — |
| Logic Array Blocks (LABs) | 1694 | — |
| Total RAM Bits | 1369728 | 1,369,728 |
| Number of I/O | 500 | 500 |
| DSP Blocks | 12 (per datasheet, family range) | — |
| Number of PLLs | 6 | [DATA_NEEDED: PLL count for S30 tier] |
| Voltage - Supply | 1.2 V core, separate I/O bank VCCIO | — |
| Temperature na Operasyon | -40C to +100C (Industrial) | 0C to +85C (commercial, 'C' speed grade) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packhaging / Kaso | 672-BBGA, FCBGA (FBGA-672) | — |
| Package Dimensions | 35 x 35 mm | — |
| Ball Pitch | 1.0 mm | — |
| Process Technology | 90 nm CMOS | 90 nm |
| Configuration | JTAG, serial, parallel (Stratix II scheme) | — |
| Level ng MSL | 3 (per JEDEC J-STD-020) | — |
| Tindminan RoHS | [DATA_NEEDED: confirm RoHS compliance on part label] | Compliant |
| Logic Elements / Cells | — | 33,880 |
| Packhaging | — | 672-BBGA, FCBGA (27x27 mm) |
| Core Voltage - Supply | — | 1.15 V to 1.25 V |
| Maximum Core Frequency (datasheet benchmark) | — | 711 MHz |
| Embedded DSP Blocks | — | 16 (Stratix II S30 tier) |
| Number of Global Clock Networks | — | [DATA_NEEDED: global clock network count] |
| Lead-Free | — | Yes |