EP3SL200H780C3 vs EP3SL200H780C3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780C3 sa pamamagitan ng Altera at EP3SL200H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP3SL200H780C3 EP3SL200H780C3N
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Manufacturer Intel (formerly Altera) —
Series Stratix III L —
Device EP3SL200 —
Packhaging 780-ball FCBGA (H780) 780-Ball FCBGA (HBGA), 29 x 29 mm
Logic Elements 200,000 200,000
Logic Array Blocks (LABs) 8,000 8,000
User I/O Pins 488 —
Embedded Memory Bits 10,901,520 10,901,504 bits
Speed Grade 3 (slowest of Stratix III bins) C3 (commercial, -3 speed)
Temperature na Operasyon Commercial grade (0C to +85C, exact range [DATA_NEEDED]) 0C to +85C (commercial)
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount
Level ng MSL 3 (168 Hours) 3
Sub-Family Stratix III L (lower-power logic variant) —
Transceivers [DATA_NEEDED: count and speed] 24 channels, up to 3.75 Gbps
DSP Blocks [DATA_NEEDED: count] 384
Tindminan RoHS [DATA_NEEDED: confirmed in datasheet] —
Lead-Free / Halogen-Free [DATA_NEEDED] —
Family — Stratix III L (low-power)
Process Node — 40 nm
User I/Os — 488
Maximum Internal Clock Frequency — 800 MHz
Voltage - Core — 0.9 V / 1.0 V (core, VCC)
Voltage - I/O — 1.2 V to 3.3 V (VCCIO banks)
Lead-Free / RoHS — Yes
Mounting Pitch — 1.0 mm ball pitch
PLLs — 12 (Stratix III PLL array)
Configuration — JTAG IEEE Std 1149.1, passive/active serial

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