EP3SL200H780C4L vs EP3SL200H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780C4L sa pamamagitan ng Intel at EP3SL200H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL200H780C4L | EP3SL200H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Series | Stratix III | — |
| Device Type | FPGA - Field Programmable Gate Array | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory | 6.5 Mbit | — |
| User I/O Count | 488 | — |
| Package Type | 780-ball FCBGA (FineLine BGA, HBGA) | — |
| Package Code | BGA-780 / PBGA780 / HBGA-780 | — |
| Package Mounting | Surface Mount | — |
| Internal Logic Frequency | up to 717 MHz (per ampheo datasheet brief) | — |
| Speed Grade | -4 (medium performance, commercial) | C3 (commercial, -3 speed) |
| Temperature na Operasyon | 0C to 85C (commercial) | 0C to +85C (commercial) |
| Lead-Free / Pb-Free | Yes (L suffix, lead-free) | — |
| Tindminan RoHS | Compliant | — |
| Process Technology | TSMC 40 nm | — |
| Configuration Modes | FPP, AS, PS, JTAG | — |
| Family | — | Stratix III L (low-power) |
| Process Node | — | 40 nm |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Packhaging | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Uri ng Pagpapasok | — | Surface Mount |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| Level ng MSL | — | 3 |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |