EP610ILI-12 vs EP610IDC-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILI-12 sa pamamagitan ng Altera at EP610IDC-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610ILI-12 EP610IDC-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Classic EPLD (EP610) —
Usable Gates 300 —
Macro Cells 16 —
Speed Grade (tpd) 12 ns —
Supply Voltage (Vcc) 5 V (4.75 V to 5.25 V) —
Supply Voltage (Vpp) [DATA_NEEDED: Vpp programming voltage] —
Operating Frequency (max) 83.3 MHz —
Logic Elements [DATA_NEEDED: exact LE count] —
User I/O Pins [DATA_NEEDED: I/O pin count] —
Dedicated Inputs 4 4
Technology CMOS EPROM CMOS, UV-erasable (windowed ceramic)
Temperature na Operasyon -40C to +85C (industrial grade) —
Packhaging 28-pin PLCC (J-Lead) —
Uri ng Pagpapasok Surface Mount Through-hole
Programmable Security Bit Yes —
TTL Compatibility 100 TTL emulation —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status of CDIP-10 variant]
Level ng MSL [DATA_NEEDED: MSL rating] —
Device Family — Altera Classic EPLD
Logic Capacity — 300 usable gates
Macrocell Count — 16 macrocells
Pin-to-Pin Logic Delay (tpd) — 10 ns
Maximum Counter Frequency (fCNT) — 100 MHz
Supply Voltage (VCC) — 5 V (nominal)
I/O Logic Compatibility — 100% TTL emulation
Package Type — 24-pin Ceramic DIP (CDIP)
I/O Pins — 20
Hanay ng Temperature na Operasyon — 0 °C to +70 °C (commercial)
Programmable Interconnect — Yes (on-chip)
In-System Programmability — Yes (via MAX+PLUS II)
Boundary-Scan Test — Yes (per device documentation)

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