EP610ILI-12 vs EP610IDC-10 比較
詳細並排比較 EP610ILI-12 由 Altera 與 EP610IDC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILI-12 | EP610IDC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD (EP610) | — |
| Usable Gates | 300 | — |
| Macro Cells | 16 | — |
| Speed Grade (tpd) | 12 ns | — |
| Supply Voltage (Vcc) | 5 V (4.75 V to 5.25 V) | — |
| Supply Voltage (Vpp) | [DATA_NEEDED: Vpp programming voltage] | — |
| Operating Frequency (max) | 83.3 MHz | — |
| Logic Elements | [DATA_NEEDED: exact LE count] | — |
| User I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Dedicated Inputs | 4 | 4 |
| Technology | CMOS EPROM | CMOS, UV-erasable (windowed ceramic) |
| 工作溫度 | -40C to +85C (industrial grade) | — |
| 封裝 | 28-pin PLCC (J-Lead) | — |
| 安裝類型 | Surface Mount | Through-hole |
| Programmable Security Bit | Yes | — |
| TTL Compatibility | 100 TTL emulation | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CDIP-10 variant] |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Device Family | — | Altera Classic EPLD |
| Logic Capacity | — | 300 usable gates |
| Macrocell Count | — | 16 macrocells |
| Pin-to-Pin Logic Delay (tpd) | — | 10 ns |
| Maximum Counter Frequency (fCNT) | — | 100 MHz |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| I/O Logic Compatibility | — | 100% TTL emulation |
| Package Type | — | 24-pin Ceramic DIP (CDIP) |
| I/O Pins | — | 20 |
| 工作溫度範圍 | — | 0 °C to +70 °C (commercial) |
| Programmable Interconnect | — | Yes (on-chip) |
| In-System Programmability | — | Yes (via MAX+PLUS II) |
| Boundary-Scan Test | — | Yes (per device documentation) |