EP610JI-30 vs EP610ILC-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610JI-30 sa pamamagitan ng Altera at EP610ILC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610JI-30 EP610ILC-25
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD (EP610) Classic EPLD (EP610 series)
Device Type UV Erasable Programmable Logic Device (EPLD) EEPLD (Electrically Erasable PLD)
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz —
Product Terms 160 160
Dedicated Inputs 4 4
I/O Pins 16 —
External Clocks 2 —
Volte ng Pagbibigay 5 V (single supply) —
Process Technology CMOS CMOS, electrically erasable
Packhaging CQCC28 (windowed ceramic JLCC, J-bend) 28-pin PLCC (J-lead)
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Temperature na Operasyon -40C to +85C (industrial, per EP610 family suffix convention) —
Uri ng Pagpapasok Surface Mount (JLCC) Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Usable Gates — 300
Maximum Operating Frequency (fMAX) — 40 MHz
Pin-to-Pin Propagation Delay (tPD) — 25 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V
Nominal Supply Voltage — 5 V
Total Inputs — 20
Bidirectional I/O Pins — 16
Hanay ng Temperature na Operasyon — 0 C to +70 C (commercial)
Programming Method — In-system, electrically erasable

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