EP610LC-15 vs EP610DC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-15 sa pamamagitan ng Altera at EP610DC-25 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP610LC-15 | EP610DC-25 |
|---|---|---|
| Brand | Altera | Rochester Electronics |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) | Altera Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | 300 |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Packhaging | 28-pin PLCC (J-lead, plastic OTP) | 24-pin CDIP (Ceramic DIP, through-hole) |
| Uri ng Pagpapasok | Surface Mount | Through Hole |
| Bilang ng Pins | 28 | — |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0 C to +70 C |
| Programming | OTP (one-time programmable) | — |
| Tindminan RoHS | unknown | — |
| Level ng MSL | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 16 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |