EP610LC-15 vs EP610DC-25 比較
詳細並排比較 EP610LC-15 由 Altera 與 EP610DC-25 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 啟用中規格比較
| 參數 | EP610LC-15 | EP610DC-25 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP610) | Altera Classic EPLD |
| Logic Elements / Macrocells | 16 macrocells | — |
| Equivalent Gates | 300 gates | 300 |
| Propagation Delay (tpd) | 15 ns | — |
| Counter Frequency (fmax) | 83.3 MHz | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (Vcc) | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| 封裝 | 28-pin PLCC (J-lead, plastic OTP) | 24-pin CDIP (Ceramic DIP, through-hole) |
| 安裝類型 | Surface Mount | Through Hole |
| 腳位數 | 28 | — |
| 工作溫度 | 0C to +70C (commercial) [DATA_NEEDED: full temperature grade] | 0 C to +70 C |
| Programming | OTP (one-time programmable) | — |
| RoHS 狀態 | unknown | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| Macrocells | — | 16 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Technology | — | CMOS EPROM (UV-erasable) |
| Programming Method | — | JEDEC fuse-map / UV-erase |
| Speed Grade Suffix | — | -25 (25 ns tPD) |