EP610LC-25 vs EP610LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-25 sa pamamagitan ng Intel at EP610LC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-25 | EP610LC-30 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD (EP610) |
| Macrocells | 16 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Volte ng Pagbibigay | 5 V ±5% | — |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| Programmability | UV-erasable (windowed package) | — |
| Packhaging | PLCC-28 | 24-pin CERDIP / PDIP |
| Temperature na Operasyon | 0C to +70C (commercial) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| I/O Pins | [DATA_NEEDED: exact I/O count] | — |
| Tindminan RoHS | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Type ng Output | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |