EP610LC-25 vs EP610LC-30 比較
詳細並排比較 EP610LC-25 由 Intel 與 EP610LC-30 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610LC-25 | EP610LC-30 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | Classic EPLD (EP610) |
| Macrocells | 16 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Toggle Frequency | 100 MHz | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| 供應電壓 | 5 V ±5% | — |
| Technology | CMOS | CMOS EPROM (UV-erasable) |
| Programmability | UV-erasable (windowed package) | — |
| 封裝 | PLCC-28 | 24-pin CERDIP / PDIP |
| 工作溫度 | 0C to +70C (commercial) | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| 安裝類型 | Surface Mount | Through-Hole |
| I/O Pins | [DATA_NEEDED: exact I/O count] | — |
| RoHS 狀態 | [DATA_NEEDED] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| 輸出類型 | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |