EP610LC-30 vs EP610JI-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-30 sa pamamagitan ng Intel at EP610JI-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610LC-30 EP610JI-30
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Classic EPLD (EP610) Altera Classic EPLD (EP610)
Macro Cells 16 —
Logic Gates Equivalent to 300 gates (typical) —
Pin-to-Pin Delay (tPD) 30 ns —
Pipelined Data Rate up to 100 MHz Up to 100 MHz
Supply Voltage (VCC) 4.75 V to 5.25 V —
Programming Voltage (VPP) 13 V nominal —
Technology CMOS EPROM (UV-erasable) —
Packhaging 24-pin CERDIP / PDIP CQCC28 (windowed ceramic JLCC, J-bend)
Temperature na Operasyon 0 C to +70 C (commercial) / -55 C to +125 C (military) -40C to +85C (industrial, per EP610 family suffix convention)
Erase/Program Cycles 1000 typical —
Uri ng Pagpapasok Through-Hole Surface Mount (JLCC)
Type ng Output CMOS tri-state (programmable) —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Logic Compatibility TTL and CMOS —
Turbo Mode Yes (registered path bypass) —
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 16
Propagation Delay (tpd) — 30 ns (max)
Product Terms — 160
Dedicated Inputs — 4
I/O Pins — 16
External Clocks — 2
Volte ng Pagbibigay — 5 V (single supply)
Process Technology — CMOS
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Lead-Free — [DATA_NEEDED: lead-free status]

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