EP610LC-30 vs EP610JI-30 比較
詳細並排比較 EP610LC-30 由 Intel 與 EP610JI-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610LC-30 | EP610JI-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD (EP610) | Altera Classic EPLD (EP610) |
| Macro Cells | 16 | — |
| Logic Gates | Equivalent to 300 gates (typical) | — |
| Pin-to-Pin Delay (tPD) | 30 ns | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Programming Voltage (VPP) | 13 V nominal | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| 封裝 | 24-pin CERDIP / PDIP | CQCC28 (windowed ceramic JLCC, J-bend) |
| 工作溫度 | 0 C to +70 C (commercial) / -55 C to +125 C (military) | -40C to +85C (industrial, per EP610 family suffix convention) |
| Erase/Program Cycles | 1000 typical | — |
| 安裝類型 | Through-Hole | Surface Mount (JLCC) |
| 輸出類型 | CMOS tri-state (programmable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| Logic Compatibility | TTL and CMOS | — |
| Turbo Mode | Yes (registered path bypass) | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 16 |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| 供應電壓 | — | 5 V (single supply) |
| Process Technology | — | CMOS |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |