EP610PC-15 vs EP610DC-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-15 sa pamamagitan ng Altera at EP610DC-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610PC-15 EP610DC-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Classic EPLD —
Device Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 300 gates —
Macrocells 16 16
Logic Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Maximum Counter Frequency 100 MHz (per family datasheet) —
Pipelined Data Rate Up to 100 MHz —
Supply Voltage (VCC) 5 V (single supply) —
Technology CMOS CMOS, EPROM-based (UV-erasable)
Architecture PAL-type, sum-of-products AND/OR array —
TTL Emulation 100% TTL compatible —
Packhaging PDIP-24 (plastic DIP, 24-pin) 24-pin CDIP (Ceramic DIP, windowed)
Bilang ng Pin 24 pins —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Uri ng Pagpapasok Through-Hole (DIP) Through-Hole
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: not stated in verified web data]
Development Tool Altera MAX+PLUS II —
Logic Test Circuitry On-board for AC/DC verification —
Device Family — Altera Classic EPLD
Maximum Pipelined Data Rate — 100 MHz
Pin-to-Pin Propagation Delay (tpd) — 10 ns
Speed Grade — -10
Volte ng Pagbibigay — 5 V (single supply)
I/O Pins — [DATA_NEEDED: exact I/O count for CDIP-24 variant]
Logic Elements — 16 macrocells (programmable AND/OR array)
Configuration Memory — UV-erasable EPROM
Reprogrammable — Yes (UV erase window on package)

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita