EP610PC-15 vs EP610DC-10 比較
詳細並排比較 EP610PC-15 由 Altera 與 EP610DC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-15 | EP610DC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | — |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 300 gates | — |
| Macrocells | 16 | 16 |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS | CMOS, EPROM-based (UV-erasable) |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| 封裝 | PDIP-24 (plastic DIP, 24-pin) | 24-pin CDIP (Ceramic DIP, windowed) |
| 腳位數 | 24 pins | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in verified web data] |
| Development Tool | Altera MAX+PLUS II | — |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| 供應電壓 | — | 5 V (single supply) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |