EP610PC-15 vs EP610PC-20T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-15 sa pamamagitan ng Altera at EP610PC-20T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610PC-15 | EP610PC-20T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Classic EPLD | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Usable Gates | 300 gates | 300 gates |
| Macrocells | 16 | — |
| Logic Delay (tPD) | 15 ns (pin-to-pin, -15 speed grade) | — |
| Maximum Counter Frequency | 100 MHz (per family datasheet) | — |
| Pipelined Data Rate | Up to 100 MHz | up to 100 MHz |
| Supply Voltage (VCC) | 5 V (single supply) | 5 V |
| Technology | CMOS | — |
| Architecture | PAL-type, sum-of-products AND/OR array | — |
| TTL Emulation | 100% TTL compatible | — |
| Packhaging | PDIP-24 (plastic DIP, 24-pin) | 24-pin PDIP (Plastic DIP) |
| Bilang ng Pin | 24 pins | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (Commercial) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | unknown |
| Development Tool | Altera MAX+PLUS II | MAX+PLUS II |
| Logic Test Circuitry | On-board for AC/DC verification | — |
| Logic Elements / Macrocells | — | 16 macrocells |
| Propagation Delay (tPD) | — | 20 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 16 |
| Number of I/O Pins | — | 16 |
| Programmable Output Enable | — | Yes (per macrocell) |
| Programming Technology | — | UV-erasable EPROM, CMOS |