EP9100C-30 vs EP910DI-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP9100C-30 sa pamamagitan ng Altera at EP910DI-30 sa pamamagitan ng Rochester Electronics. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP9100C-30 EP910DI-30
Brand Altera Rochester Electronics
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Altera Classic EPLD Classic EPLD (Altera EP910 series)
Logic Density 900 usable gates (approx.) —
Macrocells 48 —
Flip-Flops 24 —
Dedicated Inputs 24 10
Propagation Delay (tPD) 30 ns —
Maximum Toggle Frequency (fMAX) 62.5 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
I/O Standard TTL-compatible —
Technology CMOS, UV-erasable (window) or OTP CMOS, UV-erasable EPROM
Temperature na Operasyon 0C to +70C (commercial) -40C to +85C (industrial)
Packhaging 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP CDIP-40 (ceramic DIP, 40-pin with UV window)
Programming Method JEDEC via Altera APU or compatible programmer —
Uri ng Pagpapasok Through-Hole (DIP) / Surface Mount (PLCC) Through-Hole (DIP)
Tindminan RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS compliance status]
Military Grade Variant EP9100C-30/883 (MIL-STD-883 compliant) —
Product Type — UV-Erasable Programmable Logic Device (EPLD)
Macrocell Count — 24
Propagation Delay (tpd) — 30 ns
Maximum Toggle Frequency (fmax) — 62 MHz
Dedicated I/O Pins — 12 (12 input + 12 output)
Output Enable Pins — 2
Bilang ng Pin — 40
Programmable Logic Element — JEDEC fuse map (3rd-party programmer)
Manufacturer (Original) — Altera (now Intel PSG)
Current Distributor / Authorized Aftermarket — Rochester Electronics, LLC

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita