EP9100C-30 vs EP910DI-30 比較
詳細並排比較 EP9100C-30 由 Altera 與 EP910DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd規格比較
| 參數 | EP9100C-30 | EP910DI-30 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Altera Classic EPLD | Classic EPLD (Altera EP910 series) |
| Logic Density | 900 usable gates (approx.) | — |
| Macrocells | 48 | — |
| Flip-Flops | 24 | — |
| Dedicated Inputs | 24 | 10 |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Toggle Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (single supply) |
| I/O Standard | TTL-compatible | — |
| Technology | CMOS, UV-erasable (window) or OTP | CMOS, UV-erasable EPROM |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| 封裝 | 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP | CDIP-40 (ceramic DIP, 40-pin with UV window) |
| Programming Method | JEDEC via Altera APU or compatible programmer | — |
| 安裝類型 | Through-Hole (DIP) / Surface Mount (PLCC) | Through-Hole (DIP) |
| RoHS 狀態 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS compliance status] |
| Military Grade Variant | EP9100C-30/883 (MIL-STD-883 compliant) | — |
| Product Type | — | UV-Erasable Programmable Logic Device (EPLD) |
| Macrocell Count | — | 24 |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Toggle Frequency (fmax) | — | 62 MHz |
| Dedicated I/O Pins | — | 12 (12 input + 12 output) |
| Output Enable Pins | — | 2 |
| 腳位數 | — | 40 |
| Programmable Logic Element | — | JEDEC fuse map (3rd-party programmer) |
| Manufacturer (Original) | — | Altera (now Intel PSG) |
| Current Distributor / Authorized Aftermarket | — | Rochester Electronics, LLC |