EP910DC-40 vs EP910DI-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DC-40 sa pamamagitan ng Altera at EP910DI-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DC-40 EP910DI-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Aktibo
Device Family Classic EPLD (EP910 series) —
Architecture PAL-type AND/OR, UV-erasable CMOS —
Macrocells 24 24
Dedicated Inputs 12 10
Bidirectional I/O Pins 24 20
Total Inputs to Logic Array 36 —
Product Terms 240 maximum —
Maximum Propagation Delay (tPD) 40 ns —
Maximum Operating Frequency (fMAX) 25 MHz —
Global Clocks 2 —
Volte ng Pagbibigay 5 V (typical for Classic EPLD family) —
Operating Temperature (Commercial) 0 °C to 70 °C —
Packhaging DIP-40 (ceramic, through-hole) CDIP-40 (Ceramic DIP with UV window)
Uri ng Pagpapasok Through-Hole Through-Hole
Tindminan RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Programming Method UV-erase + EPROM programmer; on-board logic test circuitry EPROM programmer + JEDEC fuse map
Product Type — EPLD (Erasable Programmable Logic Device)
Family — Altera Classic EPLD
Usable Gates — 450
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) — 40 mA typical
Total Pins — 40
Temperature na Operasyon — -40C to +85C (industrial)
Technology — CMOS, UV-erasable EPROM
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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