EP910DI-35 vs EP9100C-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-35 sa pamamagitan ng Altera at EP9100C-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DI-35 EP9100C-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD Altera Classic EPLD
Macrocells 24 48
Usable Gates 450 —
Propagation Delay (tPD) 35 ns 30 ns
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 24
Bidirectional I/O Pins 20 —
Total Pins 40 —
Packhaging CDIP-40 (Ceramic DIP with UV window) 40-pin ceramic DIP (CDIP) / 44-pin PLCC (windowed) / 40-pin PDIP
Uri ng Pagpapasok Through-Hole Through-Hole (DIP) / Surface Mount (PLCC)
Temperature na Operasyon -40C to +85C (industrial) 0C to +70C (commercial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable (window) or OTP
Programming Method EPROM programmer + JEDEC fuse map JEDEC via Altera APU or compatible programmer
Erasure Method UV light through quartz window —
Tindminan RoHS [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: rohs_status]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Logic Density — 900 usable gates (approx.)
Flip-Flops — 24
Maximum Toggle Frequency (fMAX) — 62.5 MHz
I/O Standard — TTL-compatible
Military Grade Variant — EP9100C-30/883 (MIL-STD-883 compliant)

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