EP910DM-40 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM-40 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DM-40 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type UV Erasable Programmable Logic Device (EPLD) —
Family Altera Classic EP910 Classic EPLD EP910
Architecture PAL-type AND/OR with global programmable interconnect bus PAL-type sum-of-products AND-OR array
Macrocells 24 24
Dedicated Inputs 36 12
Dedicated Outputs 24 —
Bidirectional I/O Lines 24 —
Product Terms 240 240
Propagation Delay (tPD) 40 ns —
External Clocks 2 —
Process Technology CMOS —
Packhaging 40-pin Ceramic DIP (Cerdip) with UV window 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole (DIP) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0 °C to +70 °C (commercial)
Volte ng Pagbibigay 5 V —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Programming Interface JEDEC-standard fuse-map / UV erasure —
Device Type — UV-Erasable CMOS PLD (PAL-type)
Usable Gates — 900 gates
I/O Pins — 24
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Programming Method — JEDEC fuse map via device programmer; UV erase
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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