EP910ILC-15N vs EP910DC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15N sa pamamagitan ng Altera at EP910DC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Pagsanggunian na paghahambing
| Parametro | EP910ILC-15N | EP910DC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| Packhaging | PLCC-44 (J-lead, surface mount) | 24-pin ceramic DIP (DC) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |