EP910ILC-15N vs EP910DC-15 比較
詳細並排比較 EP910ILC-15N 由 Altera 與 EP910DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
規格比較
| 參數 | EP910ILC-15N | EP910DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic | Altera Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | 15 ns |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V (typical) |
| User I/O Pins | 36 | — |
| Dedicated Input Pins | 16 | — |
| 封裝 | PLCC-44 (J-lead, surface mount) | 24-pin ceramic DIP (DC) |
| 安裝類型 | Surface Mount | Through-Hole |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| RoHS 狀態 | Compliant | [DATA_NEEDED: not explicitly stated in verified data] |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Device Density | — | 900 usable gates |
| Macrocells | — | 24 |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |