EP910LC-35H vs EP910DC-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910DC-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-35H EP910DC-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) —
Logic Elements 24 macrocells —
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) —
Technology CMOS, UV-erasable EPROM —
Packhaging 40-pin Ceramic DIP (H suffix) DIP-40 (ceramic, through-hole)
User I/O Pins 36 —
Dedicated Inputs 10 12
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] —
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer UV-erase + EPROM programmer; on-board logic test circuitry
Logic Levels TTL compatible —
Kuru-kuryente ng Kapayapaan [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Uri ng Pagpapasok Through-hole (Ceramic DIP) Through-Hole
Tindminan RoHS unknown [DATA_NEEDED: rohs_status]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Device Family — Classic EPLD (EP910 series)
Architecture — PAL-type AND/OR, UV-erasable CMOS
Macrocells — 24
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Product Terms — 240 maximum
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Volte ng Pagbibigay — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita