EP910LC-35H vs EP910DC-40 比較
詳細並排比較 EP910LC-35H 由 Altera 與 EP910DC-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35H | EP910DC-40 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (EP910) | — |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| 封裝 | 40-pin Ceramic DIP (H suffix) | DIP-40 (ceramic, through-hole) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | 12 |
| 工作溫度 | [DATA_NEEDED: operating temperature range grade] | — |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | UV-erase + EPROM programmer; on-board logic test circuitry |
| Logic Levels | TTL compatible | — |
| 靜態電流 | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| 安裝類型 | Through-hole (Ceramic DIP) | Through-Hole |
| RoHS 狀態 | unknown | [DATA_NEEDED: rohs_status] |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Device Family | — | Classic EPLD (EP910 series) |
| Architecture | — | PAL-type AND/OR, UV-erasable CMOS |
| Macrocells | — | 24 |
| Bidirectional I/O Pins | — | 24 |
| Total Inputs to Logic Array | — | 36 |
| Product Terms | — | 240 maximum |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Operating Frequency (fMAX) | — | 25 MHz |
| Global Clocks | — | 2 |
| 供應電壓 | — | 5 V (typical for Classic EPLD family) |
| Operating Temperature (Commercial) | — | 0 °C to 70 °C |