EP910LI44-35 vs EP910LC44-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI44-35 sa pamamagitan ng Altera at EP910LC44-35 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI44-35 | EP910LC44-35 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Device Family | Altera Classic EPLD | — |
| Series | EP910 | — |
| Architecture | PAL-type macrocell (EPLD) | PAL-type AND/OR array |
| Number of Macrocells | 24 | — |
| Number of External Clocks | 2 | — |
| Maksimum na Taktiko ng Oras | 37 MHz | — |
| Propagation Delay (tPD) | 35 ns | 35 ns (max) |
| Process Technology | CMOS | CMOS |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Bilang ng Pins | 44 | — |
| Package Type | PLCC-44 (J-lead) | — |
| Uri ng Pagpapasok | Surface Mount / Through-Hole Socket | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Programmability | UV-erasable / one-time programmable | UV-erasable (windowed ceramic) |
| Tindminan RoHS | unknown | — |
| Logic Family | Classic EPLD | — |
| Family | — | Classic EPLD (OT sub-family) |
| Macrocells | — | 24 |
| Usable Gates | — | 450 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Total Inputs | — | 36 |
| I/O Pins | — | 24 |
| Global Clocks | — | 2 |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Packhaging | — | 44-pin PLCC (J-leaded) |