EP910PC-35 vs EP910PC-0 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-35 sa pamamagitan ng Altera at EP910PC-0 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-35 | EP910PC-0 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | — |
| Volte ng Pagbibigay | 5 V | 5 V (single supply) |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Packhaging | 40-pin PDIP (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | UV-erasable / OTP |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Logic Blocks | — | 6 (4 macrocells each) |
| Speed Grade | — | -0 (slowest) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |