EP910PC-35 vs EP910PC-0 比較
詳細並排比較 EP910PC-35 由 Altera 與 EP910PC-0 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-35 | EP910PC-0 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 24 | 24 |
| I/O Pins | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| Total Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Counter Frequency | 37 MHz | — |
| Internal Performance Frequency | 100 MHz | — |
| Technology | CMOS, UV-erasable/OTP | — |
| 供應電壓 | 5 V | 5 V (single supply) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| 封裝 | 40-pin PDIP (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Architecture | PAL-type sum-of-products, AND/OR array | — |
| Programming Method | UV-erase (ceramic) / OTP (plastic), A+PLUS / MAX+PLUS tools | UV-erasable / OTP |
| Compliance / RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 900 gates |
| Logic Blocks | — | 6 (4 macrocells each) |
| Speed Grade | — | -0 (slowest) |
| Process Technology | — | CMOS |
| Logic Compatibility | — | 100% TTL emulation |