EP910PI-15T vs EP910PI-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-15T sa pamamagitan ng Altera at EP910PI-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-15T | EP910PI-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Volte ng Pagbibigay | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | — |
| Packhaging | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (Plastic DIP) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| Tindminan RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | Non-compliant (PDIP package) |
| Device | — | EP910 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Supply Voltage (VCC) | — | 5 V nominal |
| Process Technology | — | 5 V CMOS (EPROM-based) |
| Bilang ng Pin | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |