EP910PI-15T vs EP910PI-25 比較
詳細並排比較 EP910PI-15T 由 Altera 與 EP910PI-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-15T | EP910PI-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| 供應電壓 | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | — |
| Technology | CMOS EEPROM (electrically erasable) | — |
| 封裝 | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (Plastic DIP) |
| 安裝類型 | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| 工作溫度 | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | Non-compliant (PDIP package) |
| Device | — | EP910 |
| Pin-to-Pin Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 40 MHz |
| Supply Voltage (VCC) | — | 5 V nominal |
| Process Technology | — | 5 V CMOS (EPROM-based) |
| 腳位數 | — | 40 |
| Programmability | — | UV-erasable (windowed) / one-time-programmable |